Software Assisted Snoop Containment for Packet Processing Applications (Part 3 of 3)

By Vakul Garg (vakul@freescale.com) and Varun Sethi (varun.sethi@freescale.com), Senior Software Engineer, Freescale Semiconductor. This is the last post of a series of three. Please find the first post here and the second one here. 7 - Fixing the problem Using ‘perf’ tool, first we measured the number of snoops per second on control plane core with no control plane application running and the data plane paused. It was almost ‘0’. Next we measured the number of snoops per second with Read More »

Software Assisted Snoop Containment for Packet Processing Applications (Part 2 of 3)

By Vakul Garg (vakul@freescale.com) and Varun Sethi (varun.sethi@freescale.com), Senior Software Engineer, Freescale Semiconductor. This is the second post of a series of three. You can find the first post here. 4 - Generation of snoops due to packet processing When the ingress I/O controller (e.g. Ethernet) copies the frame from its DMA internal FIFO to memory, snoops are generated to invalidate copies in any of core local caches. Also when the frame headers are brought inside local cache of Read More »

Software Assisted Snoop Containment for Packet Processing Applications (Part 1 of 3)

By Vakul Garg (vakul@freescale.com) and Varun Sethi (varun.sethi@freescale.com), Senior Software Engineer, Freescale Semiconductor. 1 - Introduction In case of multicore systems the cost of hardware enforced coherency increases with the increase in number of cores. This can be the attributed to the requirement of a snooping based coherent system, where each core must inspect the memory traffic for every other core. Indeed, as each of the ‘n’ nodes in a multicore system must process all other Read More »