Last week, I attended the Linley Tech Processor Conference in San Jose. This annual event is the best place to receive a comprehensive understanding of the major trends in multicore processor technology. Proceedings are available here.
All the major IP suppliers and processor vendors except Intel (AppliedMicro, ARM, Cavium Networks, Freescale, LSI, MIPS, NetLogic, Netronome, Tilera, Xelerated, Xilinx) were presenting their multicore products and roadmap. We clearly see now a segmentation of the market for multicore solutions: high end processors migrate to many cores while more integrated solutions focus on providing the best packet-per-watt ratio. It was also interesting that, while vendors gave a lot of technical details on their latest products, the information about roadmaps was very limited.
The OEM panel with technical managers from HP, Cisco, Juniper and Stoke raised software development as the main concern when choosing a multicore processor. Debugging, using multi-threading, being sure software is making the best use of the hardware capabilities etc. are all hot topics for networking software engineers. It was interesting to note Cisco comment “Unless you target the very high performance, there is not much reason to use ASICs anymore”.
Although software seems to be the main pain point, only one session of the conference was dedicated to software. I suggest the next one should include more software and system-level presentations to provide practical answers about developing applications on multicore platforms.
The second panel was about Multicore vs. NPU. As you know, technology is like a pendulum. Now, the pendulum is clearly on the multicore side. I don’t see a shift back to NPUs except maybe for niche markets. Multicore processors provide scalable performance with much more flexibility to develop applications faster.
Among all the presentations, I really liked Mike Coward’s about “Scaling Packet Processing and DPI to 100 Gigabits and Beyond”. Mike is the CTO of Continuous Computing. He provided an excellent system analysis showing the required processing capabilities of different functions in a DPI architecture. He explained how a 3-tier architecture (switching, packet processing, compute) can provide a compelling solution based on a mix of packet processor and Intel platforms.
Jeff Carmicael from LSI gave an very interesting overview “Why Next Gen Intelligent and Secure Networks will Require A New Breed Of Hardware Deep Packet Inspection (DPI) Processors” of the different solutions to implement an efficient DPI system using regex engines.
You will also want to review my presentation (from the software session) about “Turning Theoretical Multicore Performance Into Reality Through Software Innovations”.
Thanks to the Linley Group for this great event. I’m sure there will be more attendees next year because multicore technology is really gaining momentum.